The problem
Transistors stopped being the bottleneck. As front-end scaling reaches its physical limits, system performance is increasingly set by what surrounds the die: the package. Heat that can’t leave, interconnects that ring and leak, and a silicon-to-substrate expansion mismatch that tears solder joints apart, one thermal cycle at a time.
This year-long graduate sequence at Purdue was a tour of that bottleneck — simulated at every level where a package fails: mechanical, thermal, and electrical.
The stress that breaks chips
Silicon expands at roughly 2.6 ppm/°C. The organic substrates it’s mounted on expand at up to 70 ppm/°C in the z-axis. Every trip between -55 °C and 125 °C, that mismatch loads the solder microbumps connecting die to package — and they are the smallest, most numerous, least inspectable joints in the entire system.
I built a static-structural FEA of a single solder microbump under that -55 → 125 °C cycle in ANSYS, quantifying ~100 MPa of peak von Mises stress at the bump’s stress concentration and the plastic strain it accumulates per cycle — the quantity that ultimately sets fatigue life.
A stress peak in FEA is a claim, not a result. Refining the mesh from 5 µm down to 1 µm and watching the concentration converge is what turned 100 MPa from a number the solver produced into a number the joint actually sees.
Reading the industry’s answer
The second half of the project asked where the industry goes once the package is the wall. I authored a physics-based technical review of TSMC’s Integrated Fan-Out (InFO) packaging — more than 40 peer-reviewed papers from IEEE Xplore and Google Scholar (2016–2026), screened and synthesized against two governing models: junction-to-ambient thermal resistance (θja) and CTE-mismatch strain.
The review’s finding, reduced to one sentence: removing the organic substrate attacks the thermal, electrical, and mechanical failure modes simultaneously, because all three trace back to the same component.
| Constraint | What InFO does (vs. flip-chip PoP baselines) |
|---|---|
| Thermal resistance | θja reduced 12–17%, peak junction temperature ~12 °C lower |
| Leakage | Up to 29% less leakage-current waste at lower Tj |
| Power delivery | PDN impedance ~7× lower; 24–38% better eye height |
| Dielectric stress | 76–134% lower ELK stress — the CTE-mismatch failure mode |
| Form factor | Package ≤ 0.8 mm, ~20% thinner than conventional FC-PoP |
The elegant part is the causality: one removed component — the substrate — is the root cause of three separate failure modes. Finding that kind of shared root cause is the same discipline as any good debugging.
The electrical layer
Packaging is also a signal-integrity problem. In ANSYS Electronics I designed transmission lines to a 50 Ω characteristic-impedance target across ceramic and organic substrate stacks — sweeping trace width and substrate thickness to find the geometry each material demands — then extracted interconnect R/L/C, and simulated crosstalk between coupled lines and the eye diagrams that show what a data link actually survives.
Cooling the chip
The sequence closed at the system level: chip cooling analysis across thermal-interface contact resistance, two-phase immersion boiling, and heat-pipe sizing — the escalating ladder of options as package power density climbs toward the ~1 W/mm² regime that wafer-scale systems now demand.
Lessons
Every failure mode in this project lived at an interface — die to substrate, bump to pad, package to heat sink. The same lesson ThermOcean taught in hardware, relearned at the micron scale: the connection is the design, not the thing it connects.
